In recent years, as a means of realizing a smaller and multiband radio terminal at lower cost, a direct conversion reception scheme is becoming a focus of attention and a portable terminal mounted with a direct conversion reception apparatus is becoming the mainstream.
However, a widely known disadvantage of the direct conversion reception apparatus is a DC offset voltage (hereinafter “offset voltage”). That is, in the low-frequency part of the baseband frequency band after an quadrature demodulator, it is not possible to implement capacity coupling given the stabilization time after start-up of a receiver, and therefore an offset voltage of the quadrature demodulator output which is produced due to the fact that the local oscillating frequency at an input terminal of the quadrature demodulator and the input signal frequency are identical, is output multiplied by a gain of the low-frequency part, which causes circuit saturation in the low-frequency part and degradation of reception sensitivity.
Conventionally, there is an offset voltage calibration scheme, whereby an offset voltage calibration start signal is received from a digital signal processing section, the time constant of a low pass filter constituting an analog baseband circuit (low-frequency part) is reduced so as to realize high accuracy and high speed of offset voltage calibration at the same time (for example, see Patent Document 1).
FIG. 1 shows conventional reception apparatus 10. In FIG. 1, reception apparatus 10 is constructed of: variable gain amplifier 11; offset voltage calibration circuit 12 for variable gain amplifier 11; low pass filter 13; resistors 14 and capacitor 15 constituting low pass filter 13; switches 16 that separate capacitor 15 from signal wiring; analog baseband circuit 17 composed of variable gain amplifier 11 and low pass filter 13; digital signal processing section 18 that converts a signal received from analog base band circuit 17 to an audio signal or data signal and transmits an offset voltage calibration start signal to offset voltage calibration circuit 12; low noise amplifier 19; quadrature demodulator 20; and decoder 21.
A high-frequency signal received by an antenna (not shown) is amplified by low noise amplifier 19 and then distributed to two routes. A carrier having substantially the same frequency as the above high-frequency signal is supplied from a local oscillator (not shown). The above carrier, which is divided into two signals having a phase difference of 90 degrees by a phase shifter and the above high-frequency signal are mixed by quadrature demodulator 20 and frequency-converted to a baseband frequency band. The baseband signal is amplified by variable gain amplifier 11 and frequency-selected by low pass filter 13 and output to digital signal processing section 18.
When triggered by the offset voltage calibration start signal transmitted from digital signal processing section 18, this reception apparatus 10 opens switch 16 and starts the operation of offset voltage calibration circuit 12.
Furthermore, there is another conventional offset voltage calibration scheme, whereby a high-frequency block is always kept in a non-operating state during the offset voltage calibration operation and improves resistance against interferer (for example, see Patent Document 2).
FIG. 2 shows conventional reception apparatus 30. In FIG. 2, reception apparatus 30 is constructed of: antenna 31; low noise amplifier 32; local oscillators 33, 36 43; mixers 34, 37, 41, 42; bandpass filters 35, 39; switch 38; variable gain amplifier 40; phase shifter 44; A/D converters 45, 46, 50; offset voltage calibration circuits 47, 48; log amplifier 49; carrier detection circuit 51; and control circuit 52.
A high-frequency signal received by antenna 31 is amplified by low noise amplifier 32 and then converted to a first intermediate frequency by local oscillator 33, mixer 34 and band pass filter 35. The signal is further converted to a second intermediate frequency by local oscillator 36, mixer 37, bandpass filter 39 and then distributed to two routes through variable gain amplifier 40. The signal is then mixed with a carrier having substantially the same frequency as the second intermediate frequency supplied from local oscillator 43 at mixers 41, 42 and frequency-converted to a baseband frequency band.
In such reception apparatus 30, control circuit 52 generates control signals for switch 38, offset voltage calibration circuits 47, 48, based on a frame synchronizing signal output from a digital signal processing section (not shown). During the offset voltage calibration operation by offset voltage calibration circuits 47, 48, switch 38 is open so that mixer 37 is in a non-operating state and the leakage of interferer to mixer 37 and subsequent circuitry is reduced.
Furthermore, there is yet another conventional offset voltage calibration scheme, whereby a high-frequency block is kept in a non-operating state during the offset voltage calibration operation, thereby improving resistance against interferer, and whereby an impedance compensation circuit is provided additionally to suppress the residual offset voltage produced due to the fact that the high-frequency block operating state differs between the time of calibration operation and the time of reception operation (see, for example, Patent Document 3).
FIG. 3 shows conventional reception apparatus 60.
In FIG. 3, reception apparatus 60 is constructed of: high-frequency block 61; power supply 62 for high-frequency block 61; baseband signal processing block 63; quadrature demodulator 64; impedance compensation block 65; antenna 66; first local oscillator 67; phase shifter 68; second local oscillator 69; quadrature modulator 70; phase shifter 71; third local oscillator 72; offset voltage detection block 73; offset voltage calibration control block 74; bandpass filter 75; limiter amplifier 76; and demodulator 77.
During the offset voltage calibration operation of baseband signal processing block 63, bias supply from power supply 62 to high-frequency block 61 is stopped, so that high-frequency block 61 is in a non-operating state to reduce and the leakage of interferer to subsequent circuitry is reduced. After the offset voltage calibration operation is completed, a bias is supplied from power supply 62 to high-frequency block 61 to set high-frequency block 61 in an operating state, and therefore the output impedance of high-frequency block 61 fluctuates compared to the time of calibration operation. Meanwhile, the amount of local oscillation signal leaked to the input terminal of quadrature demodulator 64 and then reflected toward quadrature demodulator 64 changes, and the fluctuation of the offset voltage at the output terminal of quadrature demodulator 64, that is, the residual offset voltage caused by the variation in the amount of mixing, is generated. This conventional example is intended to stabilize the output impedance of high-frequency block 61 which differs between the time of calibration operation and the time of reception operation, and suppresses the above residual offset voltage by connecting impedance compensation block 65 between high-frequency block 61 and quadrature demodulator 64.
Furthermore, there is still another conventional offset voltage calibration scheme, whereby in order to restrain the residual offset voltage caused by the difference in the operating state of a high-frequency block between the time of calibration operation and the time of reception operation, a dummy circuit having the same circuit configuration as a low noise amplifier is provided additionally, one of the circuits is set in an operating state and the other circuit is set in a non-operating state during both the time of calibration operation and the time of reception operation, and the reflection coefficient between the low noise amplifier and the quadrature demodulator is thereby stabilized (see, for example, Patent Document 4).
FIG. 4 shows conventional reception apparatus 80. In FIG. 4, reception apparatus 80 is constructed of: low noise amplifier 81 that amplifies a received signal; dummy low noise amplifier (hereinafter “dummy LNA”) 82 that separates an input terminal from an outside terminal to which a received signal is input; antenna 83; bandpass filter 84; reference current generation circuit 85; and quadrature demodulator 86 that implements frequency transformation to a baseband frequency band.
Low noise amplifier 81 is set in a non-operating state during the offset voltage calibration operation and low noise amplifier 81 is in an operating state during the reception operation after the calibration operation is completed, and resistance to interferer during the calibration operation is thereby improved. Here, in order to stabilize the output impedance of low noise amplifier 81 that differs between the time of calibration operation and the time of reception operation, the output terminal of dummy LNA 82 is connected to a connection midpoint between the output terminal of low noise amplifier 81 and the input terminal of quadrature demodulator 86 and the next operation switching is performed. That is, the residual offset voltage is suppressed by setting low noise amplifier 81 in a non-operating state and dummy LNA 82 in an operating state during the calibration operation, while setting low noise amplifier 81 in an operating state and dummy LNA 82 in a non-operating state during the reception operation.
Here, restraining the degradation in reception sensitivity requires highly accurate offset voltage calibration. Furthermore, the basic operation (operating mode) of the reception apparatus shifts from an idle mode (standby mode), to a start-up mode of starting a reference current circuit and a local oscillator of each reception section, and then, after a gain setting is performed by again setting section and an offset voltage calibration operation is carried out, shifts to a reception mode and finally returns to an idle mode. If the offset voltage calibration operation can be realized fast, it is possible to shorten the operation time of the reception apparatus—that is, extend the standby time. Therefore, the offset voltage needs to be calibrated fast. On the other hand, when a filter with a large time constant exists in a feedback loop of the calibration circuit, delay is produced in the filter section, making it difficult to implement high-speed calibration.    Patent Document 1: Japanese Patent Application Laid-Open No. 2001-211098    Patent Document 2: Japanese Patent Application Laid-Open No. 2000-92143    Patent Document 3: Japanese Patent Application Laid-Open No. 2001-245007    Patent Document 4: Japanese Patent Application Laid-Open No. 2002-217769